Parallel In Serial Out Shift Register
- Right Click on System from Project Explorer and select VHDL Editor from the List
- Enter the following code in the workspace provided in the VHDL Editor window
- Save the file (.vhd) and compile the code using Compile & Import option from Build menu.It compiles the source file and generates wirelist (*.wrs) output file
- Output window shows the status of errors
- Click on Import button in Netlist/Wirelist Export&Import window.
- Autoplace the components by selecting Tools|Autoplace.
- Autoconnect the components by selecting menu Tools|Connections.Select option tool Autconnect all wires from Connect components
- Pcb layout creation is not possible for a schematic using vhdl as its component part includes only symbol hence couldn't pack components.
library ieee;
use ieee.std_logic_1164.all;
entity pinsoutshift is
port (clk, ce, oe, ld : in std_logic;
pin : in std_logic_vector(7 downto 0);
sout : out std_logic);
end pinsoutshift;
architecture pinsoutshift_a of pinsoutshift is
signal inet : std_logic_vector(7 downto 0);
begin
process(clk,ce,ld)
begin
if (ce = '1') then
if (clk='1') and (clk'event) then
if ld = '1' then
inet <= pin;
else
inet(0) <= inet(1);
inet(1) <= inet(2);
inet(2) <= inet(3);
inet(3) <= inet(4);
inet(4) <= inet(5);
inet(5) <= inet(6);
inet(6) <= inet(7);
inet(7) <= '0';
end if;
end if;
end if;
end process;
process(oe)
begin
if(ce = '1' and oe = '1') then
sout <= inet(0);
else
sout <= 'Z';
end if;
end process;
end pinsoutshift_a;
