library ieee, std, work;
use ieee.std_logic_1164.all;
use std.numeric_std.all;
use work.user_package.all;

entity adder is
 port (ce   : in std_logic;
       a, b : in unsigned15;
       s    : out unsigned15);
end adder;

architecture adder_a of adder is
begin		
 process (a, b, ce)
 begin
  if ce = '1' then
   s <= a + b;
  end if;
 end process;
end adder_a;
