library ieee;
use ieee.std_logic_1164.all;

entity encoder is
 port (inpt   : in std_logic_vector(8 downto 0);
       otpt   : out std_logic_vector(3 downto 0));
end encoder;	

architecture encoder_a of encoder is
 signal inet : std_logic_vector(12 downto 0);
begin		
 process (inpt)
 begin
  inet(12) <= inpt(7) nor inpt(8);

  inet(0) <= inpt(0) and (not inpt(1)) and (not inpt(3)) and (not inpt(5)) and inet(12);
  inet(1) <= inpt(2) and (not inpt(3)) and (not inpt(5)) and inet(12);
  inet(2) <= inpt(4) and (not inpt(5)) and inet(12);
  inet(3) <= inpt(6) and inet(12);
  otpt(0) <= inet(0) or inet(1) or inet(2) or inet(3) or inpt(8);   

  inet(4) <= inpt(1) and (not inpt(3)) and (not inpt(4)) and inet(12);
  inet(5) <= inpt(2) and (not inpt(3)) and (not inpt(4)) and inet(12);
  inet(6) <= inpt(5) and inet(12);
  inet(7) <= inpt(6) and inet(12);
  otpt(1) <= inet(4) or inet(5) or inet(6) or inet(7);   

  inet(8) <= inpt(3) and inet(12);
  inet(9) <= inpt(4) and inet(12);
  inet(10) <= inpt(5) and inet(12);
  inet(11) <= inpt(6) and inet(12);
  otpt(2) <= inet(8) or inet(9) or inet(10) or inet(11);   

  otpt(3) <= inpt(7) or inpt(8);
 end process;
end encoder_a;			
