library ieee;
use ieee.std_logic_1164.all;

entity mux16 is
 port (ce, oe : in  std_logic;
       ctrl   : in std_logic_vector (3 downto 0);
       inpt   : in std_logic_vector (15 downto 0);
       otpt   : out std_logic);
end mux16;	

architecture mux16_a of mux16 is
 signal inet : std_logic_vector (15 downto 0);
begin		
 process (ce)
 begin
  if ce = '1' then
   for i in 0 to 15 loop
    inet(i) <= inpt(i);
   end loop;
  end if;
 end process; 

 process (ctrl, oe, inet)
 begin	
  if oe = '1' then
   case ctrl is
    when "0000" => otpt <= inet(0);
    when "0001" => otpt <= inet(1);
    when "0010" => otpt <= inet(2);
    when "0011" => otpt <= inet(3);
    when "0100" => otpt <= inet(4);
    when "0101" => otpt <= inet(5);		
    when "0110" => otpt <= inet(6);
    when "0111" => otpt <= inet(7);
    when "1000" => otpt <= inet(8);
    when "1001" => otpt <= inet(9);		
    when "1010" => otpt <= inet(10);
    when "1011" => otpt <= inet(11);
    when "1100" => otpt <= inet(12);
    when "1101" => otpt <= inet(13);		
    when "1110" => otpt <= inet(14);
    when "1111" => otpt <= inet(15);
    when others => otpt <= null;		
   end case;
  else
   otpt <= 'Z';
  end if;
 end process;
end mux16_a;	
