library ieee;
use ieee.std_logic_1164.all;

entity sinsoutshift is
 port (clk, d0, ce, oe  : in std_logic;
       q7               : out std_logic);
end sinsoutshift;	

architecture sinsoutshift_a of sinsoutshift is
signal inet : std_logic_vector (0 to 7);	
begin	
 process (clk, ce)	
 begin
  if ce = '1' then
   if (clk = '1') and (clk'event) then	
    inet(7) <= inet(6);
    inet(6) <= inet(5);
    inet(5) <= inet(4);
    inet(4) <= inet(3);
    inet(3) <= inet(2);
    inet(2) <= inet(1);
    inet(1) <= inet(0);
    inet(0) <= d0;
   end if;	 
  end if;
 end process;

 process (ce, oe)	
 begin
  if (oe = '1') and (ce = '1') then
   q7 <= inet(7);
  else
   q7 <= 'Z';
  end if;
 end process;
end sinsoutshift_a;	
