library ieee, std;
use ieee.std_logic_1164.all;
use std.numeric_std.all;

entity comp is
 port (a, b            : in signed(2 downto 0);
       eq, eqi, gt, lt : out boolean);
end entity comp;

architecture behave of comp is
begin
 process (a, b)
 begin
  eq <= a = b;
  eqi <= a /= b;
  gt <= a > b;
  lt <= a < b;
 end process;
end behave;
