library ieee, std;
use ieee.std_logic_1164.all;
use std.numeric_std.all;

entity comp is
 port (a, b       : in unsigned (3 downto 0);
       eq, gt, lt : out std_logic);
end entity comp;

architecture behave of comp is
begin
 process (a, b)
 begin
  if a = b then
   eq <= '1';
   lt <= '0';
   gt <= '0';
  elsif a < b then
   eq <= '0';
   lt <= '1';
   gt <= '0';
  else
   eq <= '0';
   lt <= '0';
   gt <= '1';
  end if;
 end process;
end architecture behave;
