library ieee;
use ieee.std_logic_1164.all;

entity counter is
   port (ce, oe, clk : in std_logic;
         q           : out std_logic_vector(7 downto 0));
end counter;

architecture counter_a of counter is
   signal inet    : std_logic_vector(7 downto 0);
   signal clk_int : std_logic;                              
begin
   process (ce, clk) 
   begin
      if ce = '1' then
         clk_int <= clk;
      end if;
   end process;

   process (ce, clk_int)
   begin
      if falling_edge(clk_int) then 
         inet(0) <= not inet(0);
      end if;
   end process;

   process (ce, inet(0)) 
   begin
      if falling_edge(inet(0)) then
         inet(1) <= not inet(1);
      end if;
   end process;

   process (ce, inet(1))  
   begin
      if falling_edge(inet(1)) then
         inet(2) <= not inet(2);
      end if;
   end process;

   process (ce, inet(2))  
   begin
      if falling_edge(inet(2)) then
         inet(3) <= not inet(3);
      end if;
   end process;

   process (ce, inet(3))  
   begin
      if falling_edge(inet(3)) then
         inet(4) <= not inet(4);
      end if;
   end process;

   process (ce, inet(4))  
   begin
      if falling_edge(inet(4)) then
         inet(5) <= not inet(5);
      end if;
   end process;

   process (ce, inet(5))  
   begin
      if falling_edge(inet(5)) then
         inet(6) <= not inet(6);
      end if;
   end process;

   process (ce, inet(6))  
   begin
      if falling_edge(inet(6)) then
         inet(7) <= not inet(7);
      end if;
   end process;

   process (ce, oe)  
   begin
    for i in 0 to 7 loop
     if oe = '1' then
      q(i) <= inet(i); 
     else
      q(i) <= 'Z';     
     end if;
    end loop;
   end process;
end counter_a;
