library ieee;
use ieee.std_logic_1164.all;

entity gray is
 port (ce, oe : in std_logic;
       inpt   : in std_logic_vector(7 downto 0);
       otpt   : out std_logic_vector(7 downto 0));
end gray;	

architecture gray_8 of gray is
 signal inet : std_logic_vector(7 downto 0);
begin		
 process (ce, inpt)
 begin
  if ce = '1' then
   inet(7) <= inpt(7);
   for i in 0 to 6 loop
    inet(i) <= inpt(i+1) xor inpt(i);
   end loop;
  end if;
 end process;

 process (oe)
 begin
  if oe = '1' then
   for i in 0 to 7 loop
    otpt(i) <= inet(i);
   end loop;
  else
    otpt <= "ZZZZZZZZ";
  end if;
 end process;
end gray_8;			
