library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;

package pkg_array_8x8 is
 type array_8x8 is array( 0 to 7 ) of std_logic_vector( 7 downto 0 ) ;
end pkg_array_8x8 ;

library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;

use work.pkg_array_8x8.all ;

entity rotate_8x8 is
 port
 (
  en  : in   std_logic ;
  din  : in   array_8x8 ;
  dout : out   array_8x8
 ) ;
end rotate_8x8 ;
architecture behave of rotate_8x8 is
begin
 p_dout : process( en, din )
  if( en = '1' ) then
   for idx in dout'range loop
    dout( ( idx + 1 ) MOD 8 ) <= din( idx ) ;
   end loop ;
  else
   for idx in dout'range loop
    dout( idx ) <= din( idx ) ;
   end loop ;
  end if ;
 end process p_dout ;
end ;
