library ieee;
use ieee.std_logic_1164.all;

entity decoder is
 port (ce, bl : in std_logic;
       inpt   : in std_logic_vector (3 downto 0);
       otpt   : out std_logic_vector (6 downto 0));
end decoder;

architecture decoder_a of decoder is
begin 
 process (ce, bl, inpt)  
 begin
  if bl = '0' then
   if ce = '1' then
    case inpt is
     when "0000" => otpt <= "0111111";
     when "0001" => otpt <= "0110000";
     when "0010" => otpt <= "1011011";
     when "0011" => otpt <= "1001111";
     when "0100" => otpt <= "1100110";
     when "0101" => otpt <= "1101101";
     when "0110" => otpt <= "1111101";
     when "0111" => otpt <= "0000111";
     when "1000" => otpt <= "1111111";
     when "1001" => otpt <= "1101111";
     when "1010" => otpt <= "1110111";
     when "1011" => otpt <= "1111100";
     when "1100" => otpt <= "0111001";
     when "1101" => otpt <= "1011110";
     when "1110" => otpt <= "1111001";
     when "1111" => otpt <= "1110001";
     when others => otpt <= null;
    end case;
   end if;
  else
   otpt <= "0000000";
  end if;
 end process;
end decoder_a;
