library ieee;
use ieee.std_logic_1164.all;

package SB_to_BCD_pkg is

   type bcd_array is array(integer range <>) of std_ulogic_vector(3 
downto 0);

   function to_bcd(sb : std_ulogic_vector) return bcd_array;

end package SB_to_BCD_pkg;

package body SB_to_BCD_pkg is

   function to_bcd(sb : std_ulogic_vector) return bcd_array is
     variable result : bcd_array(sb'reverse_range);
   begin
     -- Do conversion
     return result;
   end to_bcd;

end package body SB_to_BCD_pkg;

library ieee;
use ieee.std_logic_1164.all;

use work.SB_to_BCD_pkg.all;

entity SB_to_BCD is

   generic (
     N : integer := 4);

   port (
     bcd   : out bcd_array(0 to N - 1);
     sb    : in  std_ulogic_vector(N - 1 downto 0);
     ready : in  std_ulogic;
     clock : in  std_ulogic;
     reset : in  std_ulogic);

end entity SB_to_BCD;

architecture behavior of SB_to_BCD is
begin

   process (clock, reset)
   begin
     if reset = '1' then
       bcd <= (others => (others => '0'));
     elsif rising_edge(clock) then
       if ready = '1' then
         bcd <= to_bcd(sb);
       end if;
     end if;
   end process;

end architecture behavior;
