CUPL Netlist
This option exports the netlist of the current project to the CUPL format. Select this option from the list of Export and point to the location where the output file (*.pld) should lie. To export the contents, click on the Export button. If the check box for View output file is active, the file is displayed in EDWinXP Viewer.
Xilinx Netlist
This option exports the netlist of the current project to the XILINX format. Select this option from the list of Export and point to the location where the output file (*.edn) should lie. To export the contents, click on the EXPORT button. The file is displayed in EDWinXP Viewer if the check box for View output file is checked.
Activate Insert I/O buffers if the selected vhdl module is the topmost module of the design.
EDWinXP can output to the following Xilinx output formats
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1. Xilinx 3000 series 2. Xilinx 4000E series 3. Xilinx 4000X series 4. Xilinx 5200 series 5. Xilinx 9000 series 6. Xilinx Spartan series |
7. Xilinx SpartanXL series 8. Xilinx Spartan2 series 9. Xilinx Virtex series 10. Xilinx VirtexE series 11. Xilinx Virtex2 series |
JEDEC Netlist
Export the netlist of the current project to JEDEC format. Select this option from the list of Export and point to the location where the output file (*.jed) should lie. To export the contents, click on the Export button. The file is displayed in EDWinXP Viewer if the check box for View output file is checked Activate Map output file name to view the assignment of VHDL ports to the physical pins of the target PAL device.
EDWinXP can output to the following JEDEC output formats
1. 16L8
2. 16N8
3. 16R4
4. 16R6
5. 16R8